1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and apparatus that facilitates sampling instructions for performance analysis purposes on a processor that supports speculative execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically stalled (and therefore idle), performing no useful work.
A number of forms of “speculative execution” have been proposed or are presently used to prevent the processor from stalling when a cache miss occurs. Some processors support “out-of-order execution,” in which instructions are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed generating a checkpoint and entering a “scout mode” during processor stall conditions. In scout mode, instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed 19 Dec. 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. By avoiding the need to re-order instructions that were issued out-of-order, the scout mode technique avoids the need for complex instruction control structures. However, the scout mode technique suffers from the disadvantage of having to re-compute results of computational operations that were performed during scout mode.
To avoid performing some of these re-computations, processor designers have proposed entering an “execute-ahead” mode when the processor encounters a data-dependent stall condition. In execute-ahead mode, the processor defers instructions that cannot be executed because of unresolved data dependencies and executes other non-deferred instructions in program order.
When a data dependency is ultimately resolved, the processor transitions to a “deferred mode” to execute the deferred instructions. In deferred mode, the processor executes deferred instructions that are able to be executed while re-deferring deferred instructions that still cannot be executed because of unresolved data dependencies. For example, see U.S. patent application Ser. No. 10/686,061, filed 14 Oct. 2003, entitled, “Selectively Deferring the Execution of Instructions with Unresolved Data Dependencies as They Are Issued in Program Order,” by inventors Shailender Chaudhry and Marc Tremblay.
To achieve good performance, it is desirable to be able to evaluate the performance of processor designs that support the above-described speculative-execution techniques while executing real program code. Unfortunately, it can be difficult to accurately evaluate the performance of such a processor in execute-ahead mode. In a typical performance evaluation system, the processor monitors the behavior of selected instructions in the program code as they execute on the processor. After observing the selected instructions, a designer or a programmer can extrapolate these observations to determine a statistical execution profile for the processor while executing the program code. For example, the observations can be used to determine the average number of cycles required to execute a section of the program code or the average memory latency of the program code by monitoring the execution of a small percentage of the instructions in the program code. This performance evaluation technique has proven to be reasonably accurate because most instructions proceed through the pipeline in a regular way.
However, during execute-ahead mode some of the instructions may spend an unknown number of cycles in the deferred queue, awaiting the resolution of the data dependency before they are able to complete. Consequently, monitoring a small percentage of selected instructions during execute-ahead mode can produce highly variable performance results that are likely to be inaccurate.
When such performance results are inaccurate, the users of the performance results, such as processor designers, programmers, operating systems, or compilers, can use these inaccurate performance results to make design decisions which can lead to sub-optimal system performance.
Hence, what is needed is a technique for evaluating the performance of a processor that supports speculative execution without the above-described problems.